1. Field of the Invention
The present invention relates to memory addressing and more specifically to the search in a memory of data by a computer device such as a microcontroller.
2. Discussion of the Related Art
FIG. 1 schematically shows the structure of a conventional microcontroller. Microcontroller 1 includes an FPC program controller (“Fetch and Pipeline Controller”), an address unit ADU, and an FXU unit (“FiXed point Unit”).
Program controller FPC is connected to a program memory 3 external to the microcontroller via a program memory controller 5, also external to the microcontroller. Program controller FPC includes a pre-fetch unit 7 which, in a clock cycle, stores the current instruction and ensures the microcontroller sequencing. Program controller FPC also includes a fetch and decode unit 9. For each new clock cycle, the content of unit 7 is transferred to unit 9. Thus, in a cycle n, unit 9 contains the instruction of the preceding cycle, n−1, and decodes it. The decoding of the instruction of cycle n−1 enables knowing the nature of the operation to be performed, the address in coded form of the operand(s) to be used in the operation and the address in coded form of the memory location where the result of the operation is to be placed.
Address unit ADU first includes an address decoding unit 11. For each new cycle, fetch and decode unit 9 transfers its content to address decoding unit 11. Unit 11 decodes the coded addresses that it receives, that is, it determines, based on these addresses, the physical address or real address of the operands to be fetched from the memory, as well as the physical address of the location where the result of the operation is to be stored.
Address unit ADU then includes a unit 13 enabling access in read mode to the memory support containing the operands. Conventionally, microcontroller 1 includes two internal data memories, a RAM 15 accessible via a memory controller 17 and a bank of directly accessible registers 19. A portion of memory 15 is assigned to a batch addressed by a batch pointer. As soon as unit 11 has finished decoding the addresses to be used (and performing several processings which will be discussed hereafter), it transfers its content to read access unit 13. Unit 13 then reads, at the beginning of a cycle, from the appropriate memory and fetches the operands to be used. This operation, which lasts for one cycle, is symbolized by arrows 21 and 22 respectively going from controller 17 and register bank 19 to unit 13. one cycle, is symbolized by arrows 21 and 22 respectively going from controller 17 and register bank 19 to unit 13.
At the next cycle, unit 13 transfers its content into an execution unit 23, which is the only unit of unit FXU. Unit 23 performs the arithmetic or logic operations required by the instruction and provides the result of the operation. Unit 23 then transfers the result of the operation and the physical address at which the result is to be stored to a rewrite unit 25. Unit 23 can directly have access to a register of register bank 19 in the write mode, which is symbolized by arrow 24. For example, unit 23 can modify, if required, the content of a register of the bank used as an address pointer.
Rewrite unit 25 also belongs to address unit ADU. It addresses memory 15 in write mode, which is symbolized by arrow 26, to store therein the result of the operation. Unit 25 can also address a register of register bank 19, as symbolized by arrow 27, to store therein the result, if required. Unit 25 performs its task in one clock cycle.
Units 7, 9, 11, 13, 23, and 25 of the microcontroller (these units could be called “stages”) form a so-called pipeline structure, that is, a structure in which the content of a unit is sequentially transferred to the next unit. The microcontroller thus contains six instructions at the same time, in various stages of processing. If each unit only used one clock cycle to perform its task, the processing of an instruction would take no longer than six cycles and the microcontroller would operate optimally.
In practice, however, a limitation comes from address unit ADU, and in particular from address decoding unit 11. Indeed, as will be seen hereafter, some addresses require a significant decoding time and unit 11 requires two clock cycles to provide the corresponding physical addresses. This results in the loss of a cycle and the microcontroller operation is not optimal.
An object of the present invention is to provide a shorter memory addressing method than in prior art.